Jay Yan

A FPGA developer

About Me

I am a FPGA design engineer with experience in real time data processing and embedded system design. I am familiar with traditional RTL level FPGA design using SystemVerilog/VHDL and C/C++ based high level synthesis flow.

Work Experience

August 2018 to Present Senior Electronic(FPGA) Engineer
NCR Financial Solution Group, Dundee, UK

I am responsible for FPGA-based sensor fusion solution for cash/check deposit devices.

Contributions:

  1. Proprietary image sensor controllers in FPGA.
  2. Proprietary DRAM controller for image processing in FPGA.
  3. Applying formal verification flow to designs. The tool used is symbiyosys.
  4. System Verilog /UVM based simulation environment.
  5. Exploring edge computing architecture for next generation products.

September 2014 to August 2018 Lead Electronic Hardware Engineer
General Electric (GE Power), Stafford, UK

I was responsible for FPGA-based hardware acceleration for grids protection applications. The FPGA device used was Xilinx Zynq UltraScale+.

Contributions:

  1. Analyse system level requirements, explore the feasibility and performance of using FPGA and provide FPGA-based design specifications.
  2. Implement IO interface to connect FPGA to real world, including standard IO protocols such as Ethernet, EtherCAT, AXI, etc. also customized protocols which use SERDES and transceivers.
  3. Implement solutions in MATLAB or C as golden references.
  4. Implement signal processing algorithms in FPGA, including IIR/FIR filter, interpolation, DFT. Some of the algorithms were developed in Vivado HLS (C based high level synthesis flow). Others were written in VHDL.
  5. Build FPGA simulation environment by using SystemVerilog and UVM. 1.Integrate FPGA with software, including writing test applications to access FPGA private memory space or shared DDR memory and validate implemented functions in bare-metal and Linux environment.
  6. FPGA source code management by using GIT and also FPGA project automation by using TCL script.

December 2004 to July 2013 Electronic Engineer
Huawei Technologies, Shenzhen, China

I was responsible for designing embedded hardware platforms with FPGA and embedded processors. These platforms were used for digital TV live broadcasting. The FPGA devices that we used were Xilinx Vertex 4/5 and Altera Cyclone II/III.

Contributions:

  1. Modelling and implementing program clock reference tracking method when MEPG-2 TS packets are streamed over IP network. Basically, a feasible way for FPGA to track hundreds of TV programs time reference.
  2. Implementing video processing algorithms in FPGA. Original algorithms were written in C and had to be manually redesigned and translated into Verilog.
  3. Supporting customers to solve issues and providing system solutions. For example, the IPTV head-end project including 600 SD channels and 100 HD channels for Etisalat UAE.
  4. Designing hardware schematic and debugging.

Education

September 2013 to September 2014 MSc with Distinction, System-On-Chip
University of Southampton, UK

September 2000 to July 2004 BEng, Electronic Engineering
Hefei University of Technology, China